Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines

We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allowing input signals to arrive at a pipe stage after the clock tick. We show a robust way of placing "roadblocks" (equivalent to slave latches) in each pipe stage to maintain the optimal clock rate. As explicit latches are not required at the pipe stage boundaries, the latch overhead is eliminated. We use the self-resetting scheme to circumvent often performance-limiting precharge timing requirements. We also address several issues regarding the testability of self-resetting domino circuits including scan register design and multiple stuck fault testing.

• Type: Conference
• Year: 1999
• Where: ARVLSI
• Authors: Ayoob E. Dooply, Kenneth Y. Yun
• Keywords: ARVLSI 1999, Clock, Optimal Clock Rate, Pipe Stage, VLSI