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ASPDAC
2001
ACM

Optimal spacing and capacitance padding for general clock structures

13 years 7 months ago
Optimal spacing and capacitance padding for general clock structures
Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming approaches are often trapped at local minimum and have no guarantee of obtaining global optimal solution. In this paper, we present optimal clock tuning algorithms which effectively apply capacitance-padding to reduce clock skew, power, and delay for general clock topologies. Capacitancepadding can be achieved by wire-spacing, wire-splitting, wirepadding and transistor-padding. We show that under the Elmore delay model, capacitance-padding can be formulated as a linear programming problem and solved with great efficiency. Capacitance-padding can also be used as a post processing step for any non-zero-skew clock tree or mesh structure to achieve timing closure. Experiment results on several practical industry examples show that our algorithms are extremely efficient. Problems with over
Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
Added 23 Aug 2010
Updated 23 Aug 2010
Type Conference
Year 2001
Where ASPDAC
Authors Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
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