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ISCAS
2007
IEEE

Optimal Synthesis of MITE Translinear Loops

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Optimal Synthesis of MITE Translinear Loops
— A procedure for synthesizing multiple-input translinear element (MITE) networks that implement a given system of translinear–loop equations (STLE) is presented. The minimum number of MITEs required for implementing the STLE, which is equal to the number of current variables in the STLE, is attained. The number of input gates of the MITEs is minimal amongst those MITE networks that satisfy the STLE and have the minimum number of MITEs. The synthesized MITE networks have an unique operating point and, in many cases, the network is guaranteed to be stable in a particular sense. This synthesis procedure exploits the relationship between MITE product–of–power–law (POPL) networks and linear diophantine equations which is explored in detail here.
Shyam Subramanian, David V. Anderson, Paul E. Hasl
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISCAS
Authors Shyam Subramanian, David V. Anderson, Paul E. Hasler, Bradley A. Minch
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