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ICCAD
2002
IEEE

Optimization of a fully integrated low power CMOS GPS receiver

14 years 16 days ago
Optimization of a fully integrated low power CMOS GPS receiver
This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice level optimizations of simple building blocks and a full architecture optimization of the whole based on accurate models of the building blocks. The models of the building blocks are interpolated over the data points acquired in the Spice level simulations. The optimizer technique has been applied to the optimization of an architecture for a GPS receiver. The optimal design has been implemented in a standard 0.25µm CMOS process.
Peter J. Vancorenland, Philippe Coppejans, Wouter
Added 17 Mar 2010
Updated 17 Mar 2010
Type Conference
Year 2002
Where ICCAD
Authors Peter J. Vancorenland, Philippe Coppejans, Wouter De Cock, Paul Leroux, Michiel Steyaert
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