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FCCM
2006
IEEE

A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)

9 years 7 months ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we call SMITH1 , can solve any regular and (uniquely solvable) overdetermined linear system of equations (LSE) and is not limited to matrices of a certain structure. Besides solving LSEs, the architecture at hand can also accomplish the related problem of matrix inversion extremely fast. Its average running time for n×n binary matrices with uniformly distributed entries equals 2n (clock cycles) as opposed to about 1 4 n3 in software. The average running time remains very close to 2n for random matrices with densities much greater or lower than 0.5. The architecture has a worst-case time complexity of O(n2 ) and also a space complexity of O(n2 ). With these characteristics the architecture is particularly suited to efficiently solve medium-sized LSEs as they for example appear in the cryptanalysis of certain s...
Andrey Bogdanov, M. C. Mertens
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where FCCM
Authors Andrey Bogdanov, M. C. Mertens
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