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2006

Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic

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Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic
Abstract. Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choice, but when using a Field Programmable Gate Array (FPGA), other implementation architectures are possible. This work present a hardware implementation of a broad class of integrate and fire spiking neurons with synapse models using parallel processing and serial arithmetic. This results in very fast and compact implementations of spiking neurons on FPGA.
Benjamin Schrauwen, Jan M. Van Campenhout
Added 31 Oct 2010
Updated 31 Oct 2010
Type Conference
Year 2006
Where ESANN
Authors Benjamin Schrauwen, Jan M. Van Campenhout
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