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HIPC
2004
Springer

Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction

9 years 2 months ago
Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip inductive effects are estimated with high accuracy. In earlier work [1], we described a parallel software package for inductance extraction called ParIS, which uses a novel preconditioned iterative method to solve the dense, complex linear system of equations arising in these problems. The most computationally challenging task in ParIS involves computing dense matrix-vector products efficiently via hierarchical multipole-based approximation techniques. This paper presents a comparative study of two such techniques: a hierarchical algorithm called Hierarchical Multipole Method (HMM) and the well-known Fast Multipole Method (FMM). We investigate the performance of parallel MPI-based implementations of these algorithms on a Linux cluster. We analyze the impact of various algorithmic parameters and identify regi...
Hemant Mahawar, Vivek Sarin, Ananth Grama
Added 01 Jul 2010
Updated 01 Jul 2010
Type Conference
Year 2004
Where HIPC
Authors Hemant Mahawar, Vivek Sarin, Ananth Grama
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