Sciweavers

Share
ICCAD
2009
IEEE

A parallel preconditioning strategy for efficient transistor-level circuit simulation

9 years 8 months ago
A parallel preconditioning strategy for efficient transistor-level circuit simulation
A parallel computing approach for large-scale SPICE-accurate circuit simulation is described that is based on a new preconditioned iterative solver. The preconditioner involves the Dulmage-Mendelsohn decomposition and hypergraph partitioning. Our parallel implementation makes use of a mixed load balance, employing a different parallel partition for the matrix load and solve. Based on message-passing, our simulator was designed for large parallel computers, but here good parallel speedup in modern multi-core environments is demonstrated. Traditional circuit simulation, originally made popular by the Berkeley SPICE program, relies on sparse direct matrix solver methods and does not scale well beyond tens of thousands of unknowns. Linear systems resulting from the simulation of circuits are sparse, typically have heterogeneous non-symmetric structure, and are often ill-conditioned. Parallel circuit simulation has been investigated previously, including Basermann [2] who used a Schur-compl...
Heidi Thornquist, Eric R. Keiter, Robert J. Hoekst
Added 18 Feb 2011
Updated 18 Feb 2011
Type Journal
Year 2009
Where ICCAD
Authors Heidi Thornquist, Eric R. Keiter, Robert J. Hoekstra, David M. Day, Erik G. Boman
Comments (0)
books