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ICIP
1995
IEEE

Parallel programmable video co-processor design

14 years 6 months ago
Parallel programmable video co-processor design
Modern video applications call for computationally intensive data processing at very high data rate. In order to meet the high-performance/low-cost constraints, the stateof-the-art video processor should be a programmable design which performs various tasks in video applications without sacrificing the computational power and the manufacturing cost in exchange for such flexibility. In this paper, we present a programmable video co-processor design that is capable of performing FIR/IIR filtering, subband filtering, and most discrete orthogonal transforms (DT), for the host processor in video applications. The computational speed of this co-processor is as fast as that of ASIC designs which are optimized for individual specific applications. We also show that the system can be easily reconfigured to perform multirate FIR/IIR/DT operations at negligible hardware overhead. Hence, we can either double the processing speed on the fly based on the same processing elements, or apply this feat...
An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-C
Added 29 Oct 2009
Updated 29 Oct 2009
Type Conference
Year 1995
Where ICIP
Authors An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-Chieh Liu
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