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GLVLSI
1999
IEEE

Parallel Saturating Fractional Arithmetic Units

10 years 1 months ago
Parallel Saturating Fractional Arithmetic Units
This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC operations in parallel and accumulate the results with saturation. Specialized saturation logic ensures that the output of the dual MAC unit is identical to the result of the operations performed serially with saturation after each multiplication and each addition
Navindra Yadav, Michael J. Schulte, John Glossner
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where GLVLSI
Authors Navindra Yadav, Michael J. Schulte, John Glossner
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