Parallel-stage decoupled software pipelining

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Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and new applications to make effective use of CMPs, it is desirable that compilers automatically extract thread-level parallelism from single-threaded applications. DOALL is a popular automatic technique for looplevel parallelization employed successfully in the domains of scientific and numeric computing. While DOALL generally scales well with the number of iterations of the loop, its applicability is limited by the presence of loop-carried dependences. A parallelization technique with greater applicability is decoupled software pipelining (DSWP), which parallelizes loops even in the presence of loopcarried dependences. However, the scalability of DSWP is limited by the size of the loop body and the number of recurrences it contains, which are usually smaller than the loop iteration count. This work proposes a no...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where CGO
Authors Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J. Bridges, David I. August
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