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ISCAS
2003
IEEE

Parameterized and low power DSP core for embedded systems

9 years 4 months ago
Parameterized and low power DSP core for embedded systems
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but also shortens the time-to-market. An Embedded DSP was proposed and for better performance and flexibility we design a parameterized and low power DSP core generator, Dual MAC unit, sub-word multiplier, and some function-specific blocks are adapted to accelerate applications of communication system. The gray code addressing mode, pipeline sharing and advanced hardware looping are designed to reduce power consumption in architecture level. The generator uses graphical user interface (GUI) and can generate synthesizable verilog code of the embedded DSP core according to user’s specification.
Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-J
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISCAS
Authors Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou
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