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DAC
2008
ACM

Partial order reduction for scalable testing of systemC TLM designs

9 years 3 months ago
Partial order reduction for scalable testing of systemC TLM designs
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we focus on automatically exploring all possible behaviors of the design for a given data input. We combine static and dynamic partial order reduction techniques with SystemC semantics to intelligently explore a subset of the possible traces, while still being provably sufficient for detecting deadlocks and safety property violations. We have implemented our exploration algorithm in a framework called Satya and have applied it to a variety of examples including the TAC benchmark. Using Satya, we automatically found an assertion violation in a benchmark distributed as a part of the OSCI repository. Categories and Subject Descriptors I.6.4 [Computing Methodologies]: Simulation and Modeling--Model Validation and Analysis General Terms Algorithms, Design and Verification Keywords Partial-Order Reduction, Verification...
Sudipta Kundu, Malay K. Ganai, Rajesh Gupta
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2008
Where DAC
Authors Sudipta Kundu, Malay K. Ganai, Rajesh Gupta
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