Partial scan delay fault testing of asynchronous circuits

Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect possible delay faults in a sequential asynchronous circuit. The delays that are to be tested must be provided by the synthesis system. By using this information a set of paths in the circuit that must be tested is identified (step 1). For these paths the circuit is made acyclic by inserting at least one scan latch in every cycle (step 2). Then test patterns are generated for these paths (step 3). These test patterns consist of setup and initialization vectors and the final test vector. We provide effective procedures to solve both the initialization and the test pattern generation problem. The latter problem is solved by reduction to a classical problem of stuck-at test pattern generation for a related combinational circuit. Finally, a heuristic is proposed to determine which state variables must become pa...

• Type: Conference
• Year: 1997
• Where: ICCAD
• Authors: Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin
• Keywords: Delay Fault, Hardware, ICCAD 1997, Test Pattern, Test Pattern Generation