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A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits

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A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of different primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time.
Irith Pomeranz, Sudhakar M. Reddy
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2002
Where VLSID
Authors Irith Pomeranz, Sudhakar M. Reddy
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