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ISPD
1998
ACM

A pattern matching algorithm for verification and analysis of very large IC layouts

9 years 8 months ago
A pattern matching algorithm for verification and analysis of very large IC layouts
We propose a simple, isometry invariant pattern matching algorithm for an effective data reduction useful in layout-related data processing of very complex IC designs. The repeatable geometrical features and attributes are stored in a pattern database. Original pattern instance, or its geometrical attributes, may be quickly regenerated based both on the information stored within the pattern and position of the pattern instance. We also show preliminary results of analysis of the state-of-the-art ICs which suggest that the diversity of patterns does not significantly increase with the increase of chip size.
Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojw
Added 05 Aug 2010
Updated 05 Aug 2010
Type Conference
Year 1998
Where ISPD
Authors Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
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