Peak Power Control for a QoS Capable On-Chip Network

In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-chip networks. Communication traffic of these applications makes routers greedy to acquire more power such that the total consumed power of the network may exceed the supplied power and cause reliability problems. To ensure high performance and power constraint satisfaction, the on-chip network must have a peak power control mechanism. In this paper, we propose a credit-based peak power control scheme to assure power consumption to be under the given peak power constraint, without performance degradation. The peak power control scheme efficiently regulates each flow’s injection rate at the sender to minimize performance penalty. We have two different throttling schemes for real-time traffic and best-effort traffic; a rate-based throttling and an energy-budget based throttling, respectively. The simulation re...

• Type: Conference
• Year: 2005
• Where: ICPP
• Authors: Yuho Jin, Eun Jung Kim, Ki Hwan Yum
• Keywords: Distributed And Parallel Computing, ICPP 2005, Peak Power, Peak Power Control, Power Constraint