Performance and power optimization through data compression in Network-on-Chip architectures

The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache banks interconnected through a packet-based Network-onChip (NoC) communication fabric. Thus, the NoC plays a critical role in optimizing the performance and power consumption of such non-uniform cache-based multicore architectures. While almost all prior NoC studies have focused on the design of router microarchitectures for achieving this goal, in this paper, we explore the role of data compression on NoC performance and energy behavior. In this context, we examine two different configurations that explore combinations of storage and communication compression: (1) Cache Compression (CC) and (2) Compression in the NIC (NC). We also address techniques to hide the decompression latency by overlapping with NoC communication latency. Our simulation results with a diverse set of scientific and commercial benchmark...

• Type: Conference
• Year: 2008
• Where: HPCA
• Authors: Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijay Narayanan, Ravishankar Iyer, Mazin S. Yousif, Chita R. Das
• Keywords: Computer Architecture, HPCA 2008, NoC Communication Latency, NoC Performance, Prior Noc Studies