Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs

In this paper we present a new global router appropriate for Multichip Module MCM and dense Printed Circuit Board PCB design, which utilizes a hybrid of the classical rip-up and reroute approach, and the more recent iterative deletion 9 method. The global router addresses performance issues by utilizing recent results in high performance interconnect design, while still e ectively minimizing global congestion. With experiments on the maze-routing component of our global router, we show that the choice of routing cost functions can have a signi cant impact on nal solution quality. The results of a number of previously proposed routers may be improved dramatically by adopting the cost functions we suggest here. We also nd little evidence of the net ordering problem" when our cost functions and routing model are applied. The iterative deletion method is shown to improve global solution quality, particularly when high performance interconnect is required. We evaluate the performance ...

• Type: Conference
• Year: 1998
• Where: DAC
• Authors: Jason Cong, Patrick H. Madden
• Keywords: DAC 1998, Design Automation, Global Router, Global Router Appropriate, Router Addresses Performance