Sciweavers

Share
DAC
1994
ACM

Performance-Driven Simultaneous Place and Route for Row-Based FPGAs

9 years 5 months ago
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these at the placement level. A new performance-driven simultaneous placement / routing technique has been developed for row-based designs. Up to 28% improvements in timing and 33% in wirability have been achieved over a traditional sequential place and route system in use at Texas Instruments for several MCNC benchmark examples.
Sudip Nag, Rob A. Rutenbar
Added 09 Aug 2010
Updated 09 Aug 2010
Type Conference
Year 1994
Where DAC
Authors Sudip Nag, Rob A. Rutenbar
Comments (0)
books