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ASPLOS
1991
ACM

Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors

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Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory accesses. Several different consistency models have been proposed. These range from sequential consistency on one end, allowing very limited buffering, to release consistency on the other end, allowing extensive buffering and pipelining. The processor consistency and weak consistency models fall in between. The advantage of the less strict models is increased performance potential. The disadvantage is increased hardware complexity and a more complex programming model. To make an informed decision on the above tradeoff requires performance data for the various models. This paper addresses the issue of performance benefits from the above four consistency models. Our results are based on simulation studies done for three applications. The results show that in an environment where processor reads are blocking an...
Kourosh Gharachorloo, Anoop Gupta, John L. Henness
Added 27 Aug 2010
Updated 27 Aug 2010
Type Conference
Year 1991
Where ASPLOS
Authors Kourosh Gharachorloo, Anoop Gupta, John L. Hennessy
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