Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

11

IPPS
2006
IEEE

favoriteEmaildiscussreport

99views Distributed And Parallel Com...» more IPPS 2006»

Performance of FPGA implementation of bit-split architecture for intrusion detection systems

13 years 10 months ago

Performance of FPGA implementation of bit-split architecture for intrusion detection systems

Download halcyon.usc.edu

Hong-Jip Jung, Zachary K. Baker, Viktor K. Prasann

Real-time Traffic

Distributed And Parallel Computing | IPPS 2006 |

claim paper

Related Content

» Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs

» SPPNIDS A Sea of Processors Platform for Network Intrusion Detection Systems

» Highthroughput linkedpattern matching for intrusion detection systems

» Implementing highspeed string matching hardware for network intrusion detection systems

» Scalable multipipeline architecture for high performance multipattern string matching

» An FPGABased Network Intrusion Detection Architecture

» Regular Expression Software Deceleration for Intrusion Detection Systems

» Deep Packet Filter with Dedicated Logic and Read Only Memories

» Designing and implementing a family of intrusion detection systems

Post Info
More Details (n/a)

Added	12 Jun 2010
Updated	12 Jun 2010
Type	Conference
Year	2006
Where	IPPS
Authors	Hong-Jip Jung, Zachary K. Baker, Viktor K. Prasanna

Comments (0)