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DAC
2002
ACM

Petri net modeling of gate and interconnect delays for power estimation

13 years 2 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit is converted into a HCHPN and simulated as a Petri net to get the switching activity estimate and thus the power values. The method is accurate and is significantly faster than other simulative methods. The HCHPN yields an average error of 4.9% with respect to Hspice for the ISCAS '85 benchmark circuits. The per-pattern simulation time is about 46 times lesser than PowerMill. Categories and Subject Descriptors B.7 [Hardware]: Integrated Circuits; B.7.2 [Integrated Circuits]: Design Aids--simulation General Terms Power Measurement
Ashok K. Murugavel, N. Ranganathan
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2002
Where DAC
Authors Ashok K. Murugavel, N. Ranganathan
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