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3DIC
2009
IEEE

Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh

13 years 10 months ago
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
—The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing Through Silicon Vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The systemlevel impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuw
Added 18 May 2010
Updated 18 May 2010
Type Conference
Year 2009
Where 3DIC
Authors Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen
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