Physical Synthesis for CPLD Architectures

In this paper, we present a new synthesis feature namely, "Xor matching", and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architecture that is based on PAL-like macrocells. Our goal is to use the Xor gate and the foldback terms, (or shareable expander Altera equivalent terminology [17]), available in each macrocell for minimizing the number of macrocells required to implement a circuit. We propose two innovative approaches: the first, is a very fast algorithm which always gives a match for a function onto the Xor gate of the CPLD device, when one exists; the second approach, is based on answering a fundamental problem: determine if a given foldback cluster can be assigned to a PAL block. A foldback cluster is defined as a set of functions and sub-functions that result in the same foldback which is created by the foldback decomposition algorithm. A suite of test cases (MCNC) were tested with device-fitting algorithms targeting the Atmel CP...

• Type: Conference
• Year: 2009
• Where: CIIA
• Authors: Sid-Ahmed Senouci
• Keywords: CIIA 2009, CPLD Device, Foldback Cluster, Information Technology, Xor Gate