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ISQED
2009
IEEE

Place and route considerations for voltage interpolated designs

10 years 11 months ago
Place and route considerations for voltage interpolated designs
— Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. Its implementation in a VLSI-CAD flow has been considered through the synthesis stage. In this paper we study the implications of place and route on voltage interpolation. We evaluate multiple placement strategies, and conclude that a hybridization of forced placement and cluster boxing techniques results in minimum overhead.
Kevin Brownell, Ali Durlov Khan, David Brooks, Gu-
Added 19 May 2010
Updated 19 May 2010
Type Conference
Year 2009
Where ISQED
Authors Kevin Brownell, Ali Durlov Khan, David Brooks, Gu-Yeon Wei
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