Placement of 3D ICs with Thermal and Interlayer Via Considerations

Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during global and detailed placement. Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects. This method allows wirelengths to be minimized for any desired interlayer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayer via counts. Wirelength reductions within 2% of the optimal can be achieved using 46% fewer interlayer vias. Temperatures can be reduced by about 20% with only 1% higher wirelengths and 10% more interlayer vias. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids ? Placement and routing; B.7.1 [Integrated Circuits]: Types and Design Styles ? Advanced technologies General Terms Algorithms, Design, Experimentation, Performance Keywords...

• Type: Conference
• Year: 2007
• Where: DAC
• Authors: Brent Goplen, Sachin S. Sapatnekar
• Keywords: DAC 2007, Design Automation, Fewer Interlayer Vias, Integrated Circuits, Three-dimensional Integrated Circuits