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2000
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A Placement Algorithm for FPGA Designs with Multiple I/O Standards

12 years 3 months ago
A Placement Algorithm for FPGA Designs with Multiple I/O Standards
State-of-the-art FPGAs possess I/O resources that can be configured to support a wide variety of I/O standards [1]. In such devices, the I/O resources are grouped into banks. One of the consequences of the banked organization is that all of the I/O objects that are placed within a bank must use ,,compatible" I/O standards. The compatibility of I/O standards is based on each standard's supply and reference voltage requirements. For designs that use more than one I/O standard, the constraints associated with the banked organization lead to a constrained I/O pad placement problem. Meeting these constraints with a minimal deleterious effect on traditional objectives like minimizing wirelength turns out to be quite challenging. In this paper, we present a placement algorithm that operates in the context of these constraints. Our approach uses a combination of simulated annealing, weighted bipartite matching and constructive packing to produce a feasible I/O placement. Results show...
Jason Helge Anderson, Jim Saunders, Sudip Nag, Cha
Added 24 Aug 2010
Updated 24 Aug 2010
Type Conference
Year 2000
Where FPL
Authors Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman
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