Platform-Based Testbench Generation

This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a configurable, synthesizable testbench architecture, which can be completely mapped to emulators or FPGAs. Exploiting generic controllers and re-using protocol-specific stimuli generators combined with topology and microprogram generation is responsible for almost zero overhead compared to behavioral testbenches.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Renate Henftling, Andreas Zinn, Matthias Bauer, Wolfgang Ecker, Martin Zambaldi
• Keywords: DATE 2003, Hardware, Re-using Protocol-specific Stimuli, Real Life Example, Synthesizable Testbench Architecture