Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

11

ASPDAC
2010
ACM

favoriteEmaildiscussreport

167views Hardware» more ASPDAC 2010»

Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs

13 years 2 months ago

Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs

Download www.asp-dac.itri.org.tw

Xin Zhao, Sung Kyu Lim

Real-time Traffic

ASPDAC 2010 | Hardware |

claim paper

Related Content

» Reliability aware through silicon via planning for 3D stacked ICs

» Throughsiliconvia aware interconnect prediction and optimization for 3D stacked ICs

» Prebond testable lowpower clock tree design for 3D stacked ICs

» Faulttolerant 3D clock network

» Codesign of signal power and thermal distribution networks for 3D ICs

» Predicting the worstcase voltage violation in a 3D power network

Post Info
More Details (n/a)

Added	10 Feb 2011
Updated	10 Feb 2011
Type	Journal
Year	2010
Where	ASPDAC
Authors	Xin Zhao, Sung Kyu Lim

Comments (0)