Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices

This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of power dissipation, and both design styles and various clock gating schemes can be found in modern, high-performance processors. Although some work in the circuits domain has explored these issues from a power perspective, thermal treatments are less common, and we are not aware of any work in the architecture domain. We study both SRAM and latch and multiplexer (“latch-mux”) designs and their associated clock-gating options. Using circuitlevel simulations of both design styles, we derive power-dissipation ratios which are then used in cycle-level power/performance/thermal simulations. We find that even though the “unconstrained” power of SRAM designs is always better than latch-mux designs, latch-mux designs dissipate less power in practice when a structure’s average occupancy is low but access ra...

• Type: Conference
• Year: 2005
• Where: ISLPED
• Authors: Yingmin Li, Mark Hempstead, Patrick Mauro, David Brooks, Zhigang Hu, Kevin Skadron
• Keywords: Design, ISLPED 2005, Latch-mux Designs, Stall Gating