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DFT
2007
IEEE

Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits

10 years 9 months ago
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits
Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, various schemes to protect cryptographic devices against such attacks have been devised and some implemented in practice. Almost all of these protection schemes target an individual side-channel attack and consequently, it is not obvious whether a scheme for protecting the device against one type of sidechannel attacks may make the device more vulnerable to another type of side-channel attacks. We examine in this paper the possibility of such a negative impact for the case where fault detection circuitry is added to a device (to protect it against fault injection attacks) and analyze the resistance of the modified device to power attacks. To simplify the analysis we focus on only one component in the cryptographic device (namely, the S-box in the AES and Kasumi ciphers), and perform power attacks on the original...
Francesco Regazzoni, Thomas Eisenbarth, Johann Gro
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where DFT
Authors Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar
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