Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure

This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional delay or performance degradation. For this goal, way selection logic and specialized replacement policy are designed to enable only one way of set-associative cache as in the direct-mapped cache. Overall cache access time becomes almost the same as that of conventional set associative cache with accessing additional way selection logic. Because data array can be accessed without waiting for tag comparison, multiplexer delay can be removed totally. The simulation result shows that the proposed architecture can reduce a per access power consumption by 59% over conventional setassociative caches with average 0.06% of negligible performance loss.

• Type: Conference
• Year: 2004
• Where: ICCD
• Authors: Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim
• Keywords: Cache Block Allocation, Hardware, ICCD 2004, Overall Cache Access, Set Associative Cache