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GLVLSI
2003
IEEE

Power-aware pipelined multiplier design based on 2-dimensional pipeline gating

9 years 3 months ago
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and computer architectures. Although Boolean multipliers have natural power awareness to the changing of input precision, deeply pipelined designs do not have this benefit. A 2-dimensional pipeline gating scheme is proposed in this paper to solve this problem and improve the power awareness in these designs. 2-Dimensional pipeline gating is to gate the clock to registers in both vertical direction (data flow direction in pipeline) and horizontal direction (within each pipeline stage). This technique only needs very little additional area and the overhead is hardly noticeable. A set of array multipliers were designed and tested. Results show that the new 16-bit array multiplier using this technique has an average power saving of 66% and an average latency reduction of 47% over original design under equal input prec...
Jia Di, Jiann S. Yuan
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where GLVLSI
Authors Jia Di, Jiann S. Yuan
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