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LCPC
2004
Springer

Power-Aware Scheduling for Parallel Security Processors with Analytical Models

11 years 10 months ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS), power gating (PG), and multipledomain partitioning are regarded as effective schemes to reduce dynamic and static power. In this paper, we investigate the problem of power-aware scheduling tasks running on a scalable encryption processor, which is equipped with heterogenous distributed SOC designs and needs the effective integration of the elements of DVS, PG, and the scheduling for correlations of multiple domain resources. We propose a novel heuristic that integrates the utilization of DVS and PG and increases the total energy-saving. Furthermore, we propose an analytic model approach to make an estimate about its performance and energy requirements between different components in systems. These proposed techniques are essential and needed to perform DVS and PG on multiple domain resources which are of co...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq
Added 02 Jul 2010
Updated 02 Jul 2010
Type Conference
Year 2004
Where LCPC
Authors Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei Kuan Shih, TingTing Hwang
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