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PATMOS
2005
Springer

A Power-Efficient and Scalable Load-Store Queue Design

9 years 11 months ago
A Power-Efficient and Scalable Load-Store Queue Design
Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs a negligible performance loss of less than 0.6%.
Fernando Castro, Daniel Chaver, Luis Piñuel
Added 28 Jun 2010
Updated 28 Jun 2010
Type Conference
Year 2005
Where PATMOS
Authors Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado
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