Power minimization for dynamic PLAs

—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictable routing delay. However, the NOR–NOR structure incurs high switching activity in product lines and, thus, results in large power consumption. In this paper, we propose a new dynamic PLA structure which incorporates super product lines. A super product line adds the NAND functionality on top of the NOR structure, thus, lowering the switching activities in the product lines, as well as power consumption. Since there are many candidates for super product lines, we have developed a computer-aided design (CAD) algorithm based on the maximum weighted matching to find the optimal solution. We have performed experiments on a large set of Microelectronics Center of North Carolina (MCNC) benchmark circuits. The post simulation results show significant reduction in power consumption. Among the experimental circuits...

• Type: Conference
• Year: 2005
• Where: ASPDAC
• Authors: Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh
• Keywords: ASPDAC 2005, Hardware, Power Consumption, Product Lines, Super Product Lines