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ISCAS
1999
IEEE

Power reduction through iterative gate sizing and voltage scaling

10 years 5 months ago
Power reduction through iterative gate sizing and voltage scaling
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-level voltage scaling for those designs that are not under the strictest timing budget. An iterative framework is proposed to integrate voltage scaling with a min-separator based gate sizing to enhance power saving. The proposed methods are evaluatedusing the MCNC benchmarkcircuits. and an average of 19.12%power reduction over the circuits having only one supply voltage has been achieved.
Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, W
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where ISCAS
Authors Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
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