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DATE
2007
IEEE

Process variation tolerant low power DCT architecture

9 years 17 days ago
Process variation tolerant low power DCT architecture
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive voltage scaling by exploiting the fact that not all intermediate computations are equally important in a DCT system to obtain “good” image quality with Peak Signal to Noise Ratio(PSNR) > 30 dB. This observation has led us to propose a DCT architecture where the signal paths that are less contributive to PSNR improvement are designed to be longer than the paths that are more contributive to PSNR improvement. It should also be noted that robustness with respect to parameter variations and low power operation typically impose contradictory requirements in terms of architecture design. However, the proposed architecture lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under a scaled supply voltage and/or variations in process parameters, any possi...
Nilanjan Banerjee, Georgios Karakonstantis, Kaushi
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where DATE
Authors Nilanjan Banerjee, Georgios Karakonstantis, Kaushik Roy
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