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2001
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Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language

11 years 3 days ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningprocessor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tunedfor the application. Howevel; such a processormemory eo-exploration approach critically needs the ability to explicitly capture heterogeneous memory architectures. We present in this paper a language-based approach to explicitly capture the memory subsystem conjiguration, and pelform exploration of the memory architecture to trade-off cost versusperformance. Wepresent a set of experiments using our Memory-AwareArchitectural Description Language to drive the exploration of the memory subsystemfor the TIC621I processor architecture, demonstrating a range of cost andpelformanee attributes.
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2001
Where VLSID
Authors Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau
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