Progressive Bridge Identification

9 years 9 months ago
Progressive Bridge Identification
We present an efficient algorithm for identification of two-line bridges in combinational CMOS logic that narrows down the two-line bridge candidates based on tester responses for voltage tests. Due to the implicit enumeration of bridge sites, no layout extraction or precomputed stuck-at fault dictionaries are required. The bridge identification is easily refined using additional test pattern results when necessary. We present results for benchmark circuits and four common fault models (wiredAND, wired-OR, dominant, and composite), evaluate the diagnosis against other possible fault types, and summarize the quality of our results.
Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Bla
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ITC
Authors Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton
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