Protecting bus-based hardware IP by secret sharing

Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation is applicable to a broad category of electronic systems with a primary bus. Such designs include (1) numerous IP offerings for USB, PCI, PCI-E, AMBA and other bus standards typically used in system-on-a-chip designs and computer peripherals, (2) SRAM-based FPGAs that are programmed through an input bus, (3) general-purpose and embedded microprocessors, including soft cores, (4) DSPs, (5) network processors, and (6) game consoles. Our key insight is that such designs can be locked by scrambling the central bus by controlled reversible bit-permutations and substitutions. To securely establish a unique code per chip to control bus scrambling, we employ true random number generators and Diffie-Hellman cryptography during activation. Categories and Subject Descriptors K.5.1 [Hardware/Software Protection]: Proprieta...

• Type: Conference
• Year: 2008
• Where: DAC
• Authors: Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
• Keywords: Bus Standards, Computer Architecture, DAC 2008, Primary Bus, Work Addresses Protection