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MICRO
2002
IEEE

Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware

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Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware
abstracting the operation of lower-level packet processing functions. The library synthesizes into field-programmable gate array (FPGA) logic and is utilized in a network platform called the field-programmable port extender (FPX). The library processes asynchronous transfer mode (ATM) cells, ATM adaptation layer 5 (AAL5) frames, Internet protocol (IP) messages, and user datagram protocol (UDP) packets directly in hardware.1 Applications can process data at several layers of the protocol stack using the library of wrappers discussed in this article. Layers are important for networks because they let appliabstract from above and below details of the network protocols. At the lowest layer, networks modify raw data passing between interfaces. At higher levels, the applications process variable length frames or IP packages. For example, an Internet router or firewall uses the IP, frame, and cell wrapper together with a circuit to perform routing lookups. At the user level, a network applica...
Florian Braun, John W. Lockwood, Marcel Waldvogel
Added 22 Dec 2010
Updated 22 Dec 2010
Type Journal
Year 2002
Where MICRO
Authors Florian Braun, John W. Lockwood, Marcel Waldvogel
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