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ICCAD
2009
IEEE

PSTA-based branch and bound approach to the silicon speedpath isolation problem

9 years 1 months ago
PSTA-based branch and bound approach to the silicon speedpath isolation problem
The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The identification of speedlimiting paths, or simply speedpaths, in silicon debug is a crucial step, required for both "fixing" failing paths and for accurate learning from silicon data. We propose using characterized, presilicon, variational timing models to identify speedpaths that can best explain the observed delays from silicon measurements. Delays of all logic paths are written as affine functions of process parameters, called hyperplanes, and a branch and bound approach is then applied to find the "best" path combinations. Our method has been tested on a set of ISCAS-89 circuits and the results show that it accurately identifies the speedpaths in most cases, and that this is achieved in a very efficient manner.
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
Added 18 Feb 2011
Updated 18 Feb 2011
Type Journal
Year 2009
Where ICCAD
Authors Sari Onaissi, Khaled R. Heloue, Farid N. Najm
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