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2003
IEEE

Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization

9 years 6 months ago
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as Hanan grafting and non-Hanan sliding, and reveal generally negligible contribution of non-Hanan sliding. We propose a greedy iterative interconnect timing optimization algorithm called Q-Tree. Our experimental results show that Q-Tree starting with Steiner minimum tree topologies achieves better timing performance than C-Tree [1], PER-Steiner [5] and BA-Tree [14] algorithms. Also, executing Q-Tree starting with BA-Tree or P-Tree [13] topologies can achieve better timing performance, especially, with shorter wires and fewer buffers. In general, Q-Tree can be applied to any interconnect tree for further timing performance improvement, with practical instance sizes and easily-extended functionality - e.g., with buffer station and routing obstacle avoidance consideration.
Andrew B. Kahng, Bao Liu
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISVLSI
Authors Andrew B. Kahng, Bao Liu
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