Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard

ng precision of abstract SystemC models using the SystemC Verification Standard Franco Carbognani1 , Christopher K. Lennard2 , C. Norris Ip3 , Allan Cochrane2 , Paul Bates2 1 Cadence European Labs, 2 ARM Ltd, 3 Cadence Design Systems The increasing complexity of Systems on Chip (SoC) has ed the need for abstract executable specifications (models) covering both hardware and embedded software. The new capabilities of SystemC 2.0, such as those added for transaction-based communication and test-bench Specification and monitoring, facilitate this SoC modeling. an obstacle to the adoption of abstract modeling as standard design practice is the lack of well establishes methodologies for the assessment of model precision. We describe such a methodology based on the SystemC Verification Standard implemented by Cadence's TestBuilder-SC. This methodology enables comparison of high-level (transaction level) SoC models in SystemC against implementation RTL models. An application of the metho...

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Franco Carbognani, Christopher K. Lennard, C. Norris Ip, Allan Cochrane, Paul Bates
• Keywords: Abstract Systemc Models, DATE 2003, Hardware, SystemC, SystemC Verification