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ISCAS
2005
IEEE

Quantized LDPC decoder design for binary symmetric channels

9 years 4 months ago
Quantized LDPC decoder design for binary symmetric channels
Abstract— Binary Symmetric Channels (BSC) like the Interchip buses and the Intra-chip buses are gaining a lot of attention due to their widespread use with multimedia storage devices and on system-on-chips (SoC) respectively. While the audio and video traffic between systems has increased many-fold over the years, SoC is a reality due to the advances in technology as predicted by the Moore’s Law. These buses are prone to error arising from crosstalk between wires, propagation delay etc. Due to low latency requirements, re-transmission is undesirable in the event of an error and forward error correction (FEC) is a necessity. This paper chooses the low density parity check (LDPC) codes for FEC. Several quantization schemes to reduce the size of the decoder, and the associated code performance, are presented herein. The reduction in size due to the quantization schemes is made apparent via implementation on a Xilinx Virtex FPGA.
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where ISCAS
Authors Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
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