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FPL
2008
Springer

Rapid estimation of power consumption for hybrid FPGAs

9 years 1 months ago
Rapid estimation of power consumption for hybrid FPGAs
A hybrid FPGA consists of island-style fine-grained units and domain-specific coarse-grained units. This paper describes an approach to estimate the power consumption of a set of hybrid FPGA architectures. The dynamic power consumption of the fine-grained units is obtained using standard FPGA tools, and the coarse-grained units using standard ASIC tools. Based on this approach, the dynamic power consumption of different hybrid FPGA architectures can be studied and we report on results over a set of floating point benchmark circuits.
Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Ste
Added 26 Oct 2010
Updated 26 Oct 2010
Type Conference
Year 2008
Where FPL
Authors Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
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