Sciweavers

Share
RTAS
2006
IEEE

Real-Time Scheduling on Multicore Platforms

9 years 3 months ago
Real-Time Scheduling on Multicore Platforms
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power problems impose limits on the performance of single-core designs. Accordingly, several chip manufacturers have already released, or will soon release, chips with dual cores, and it is predicted that chips with up to 32 cores will be available within a decade. To effectively use the available processing resources on multicore platforms, software designs should avoid co-executing applications or threads that can worsen the performance of shared caches, if not thrash them. While cache-aware scheduling techniques for such platforms have been proposed for throughput-oriented applications, to the best of our knowledge, no such work has targeted real-time applications. In this paper, we propose and evaluate a cache-aware Pfair-based scheduling scheme for real-time tasks on multicore platforms.
James H. Anderson, John M. Calandrino, UmaMaheswar
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where RTAS
Authors James H. Anderson, John M. Calandrino, UmaMaheswari C. Devi
Comments (0)
books