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2006
Springer

Realistic Worst-Case Execution Time Analysis in the Context of Pervasive System Verification

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Realistic Worst-Case Execution Time Analysis in the Context of Pervasive System Verification
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP processor. We get a time triggered distributed real-time system by connecting several such ECU's via a common bus. We define a programming model for such a system at the instruction set architecture (ISA) level and prove that it is correctly implemented at the gate level. The proof combines theories of processor correctness, communication systems, program correctness and realistic worst-case execution time (WCET) analysis into a single unified mathematical theory.
Steffen Knapp, Wolfgang J. Paul
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2006
Where BIRTHDAY
Authors Steffen Knapp, Wolfgang J. Paul
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